Some serial interconnects, such as Peripheral Component Interconnect (PCI) express (PCIe), use an 8b/10b encoding scheme, which uses ten bits on the wire to represent eight bits of meaningful data. The 8b/10b encoding scheme is designed to ensure a sufficient 1-to-0 and 0-to-1 transition density such that the receiver can clock the inbound packet. That is a loss of 20% in bandwidth, due to encoding, and a 25% loss in transmission performance.
In addition to encoding the 28 possible data patterns for both positive and negative disparities, the 10-bit encodings cover some control characters (also known as K-codes) that are used for various purposes, such as determining framing boundaries. These can be broadly categorized as packet delineating K-codes and lane stream K-codes. Packet delineating K-codes denote the start or end of a packet (e.g., STP, SDP, END, EDB). On the other hand, lane stream K-codes are used independently on a per-lane basis and are used for ordered sets used during link training (training sets TS1/TS2), electrical idle entry/exit sequences (EIOS and EIES, respectively), or the periodic skipped characters (SKP) ordered sets used for tolerating parts per million (ppm) differences in the distinct clock mode. One of the lane stream K-codes (COM) is used to uniquely identify the byte alignment and is used to recover from errors such as bit slip or add. In addition to guaranteeing eventual recovery from multiple bit errors, including loss of byte alignment due to errors such as bit slip/adds, 8b/10b enables a guaranteed detection against any single bit flip error (in conjunction with CRC).
As serial link-based implementations become ubiquitous, and the frequency of those implementations continues to increase, efficient encodings become critical to extracting the most of the raw bandwidth.
Replacing 8b/10b encoding is not without risks. The challenges in the reliability of a new scheme would need to be solved. Any new scheme must be able to guarantee the existing error model, which guarantees some predetermined number of bit flip error detection and eventual recovery from other error types (including multiple bit errors, bit slips, etc.).
In addition, as the frequency increases (e.g., PCIe 3.0 at 8 GT/s), there may be other error types that need to be addressed with any new encoding scheme. For example, receiver designs that use Decision Feedback Equalizers (DFEs) should be considered. DFEs may see a single bit flip corrupt subsequent bits depending on the bit pattern. Even existing 8b/10b schemes may not be able to detect these types of errors. Thus, in addition to preserving the existing fault model, it would be highly desirable to tolerate multiple bit errors within a sliding window of bits in any lane.
For serial links that have attributes of both serial and parallel links (such as PCIe where data bytes are striped across multiple lanes in a multi-lane link), existing solutions such as 64/66 do not work. The proposed scheme addresses some of these issues.